1. Field of the Invention
The present invention relates to a DMA (direct memory access) controller for directly controlling a data transfer between memories, or the like, without the process of the CPU (central processing unit) and the control method thereof, in particular, to a DMA controller for controlling a burst access in an external bus at the time of DMA transfer between an internal bus and an external bus and the control method thereof.
2. Description of the Background Art
In recent years information processing apparatuses such as personal computers have spread widely and the demand for higher processing speed and a greater number of functions has increased. A DMA which directly carries out data transfer between memories without the process of the CPU can be cited as a function which implements a higher processing speed of an information processing apparatus. In the following, a configuration and an operation of a conventional DMA controller are described.
(Configuration of Conventional DMA Controller)
FIG. 1 is a block diagram showing a schematic configuration of a conventional DMA controller. This DMA controller includes a transfer source address register 10 for storing the transfer source address of the DMA, a transfer destination address register 11 for storing the transfer destination address of the DMA, a DMA transfer counter 12 for storing the number of bytes of the data to be DMA transferred, a DMA request selection register 13 for selecting a request signal which starts up the DMA, a DMA control unit 50 for carrying out a DMA transfer by accessing an external memory, which is not shown, a DMA request detection unit 60 for detecting a DMA request from outside in accordance with the setting of DMA request selection register 13 and a FIFO (first in first out) memory 70 for temporarily storing data read out by DMA control unit 50.
Signals 100 to 104 indicated to the left of the DMA controller are signals at the time when an external bus master such as a CPU accesses transfer source address register 10, transfer destination address register 11, DMA transfer counter 12 or DMA request selection register 13 and include a chip select (CS) signal 100 for indicating that the access is valid, 32 address (ADDR [31:0]) signals 101 for selecting the registers to be accessed, a read/write control (RW) signal 102 for indicating whether the access is a read access or a write access, 32 write data (WDATA [31:0]) signals 103 for transferring data for a write access and 32 read data (RDATA [31:0]) signals 104 for transferring data for a read access.
Signals 110 to 115 indicated to the right of the DMA controller are signals for accessing buses inside of the semiconductor chip in which the DMA controller is incorporated (hereinafter referred to as internal buses) and include 32 internal address (IADDR [31:0]) signals 110 for selecting regions to be accessed, an internal read/write control (IRW) signal 111 for indicating whether the access is a read access or a write access, 32 internal write data (IWDATA [31:0]) signals 112 for transferring data for a write access, 32 internal read data (IRDATA [31:0]) signals 113 for transferring data for a read access, an internal ready (IREADY) signal 114 for indicating that the bus access has been completed and an internal bus access request (IREQ) signal 115 for requesting the internal bus to make an access.
In addition, signals 120 to 126 indicated to the right of the DMA controller are signals for carrying out an access request to an external bus interface, which is not shown, connected to a bus (hereinafter referred to as external bus) outside of the semiconductor chip in which the DMA controller is incorporated and include 32 external address (EADDR [31:0]) signals 120 for selecting regions to be accessed, an external read/write control (ERW) signal 121 for indicating whether the access is a read access or a write access, 32 external write data (EWDATA [31:0]) signals 122 for transferring data for a write access, 32 external read data (ERDATA [31:0]) signals 123 for transferring data for a read access, an external ready (EREADY) signal 124 for indicating that the bus access has been completed, an external bus access request (EREQ) signal 125 for requesting an external bus to make an access and an external burst request (EBURST) signal 126 for requesting an external bus interface to make a burst access.
In addition, a DMA request signal (DMAREQ [31:0]) 130 for accepting a DMA request and a clock (CLK) signal 150 utilized in the entire system are included as other signals.
(Operation of Conventional DMA Controller)
(1) Setting of DMA
The setting of a DMA is carried out by the CPU by writing values in the internal registers (transfer source address register 10, transfer destination address register 11, DMA transfer counter 12 and DMA request selection register 13) of the DMA controller.
FIG. 2 is a timing chart when the CPU writes a value in the internal register of the DMA controller. The internal register receives a value of ADDR [31:0] 101 at the rising edge of CLK signal 150 in cycle 1 in the case where it is detected that CS signal 100 is at a high level (hereinafter merely denoted as “H”) and that RW signal 102 is at a low level hereinafter merely denoted as “L”). The decode result of this ADDR [31:0] 101 determines which register is accessed. Then, the value of WDATA [31:0] 112 is written into the register that is selected by the address which is received.
A transfer source address of the DMA is set in transfer source address register 10, a transfer destination address of the DMA is set in transfer destination address register 11 and the byte number of the data to be transferred by the DMA is set in DMA transfer counter 12. In addition, each bit of DMA request selection register 13 corresponds to, respectively, 32 signals included in DMAREQ [31:0] 130 and “1” is set at the bit corresponding to a signal which starts up the DMA.
(2) Start-Up of DMA
DMA request detection unit 60 starts a DMA transfer at the rising edge of a signal, from among signals included in DMAREQ [31:0] 130, which corresponds to the bit set to “1” in DMA request selection register 13. When DMA request detection unit 60 detects the rising edge, DMA control unit 50 is notified of this.
(3) Carrying Out of DMA
When a DMA request is detected by DMA request detection unit 60, DMA control unit 50 carries out a DMA transfer. FIG. 3 is an example of a timing chart of a conventional DMA controller at the time of DMA transfer. Here, transfer source address register 10 is set to “0x00000000,” transfer destination address register 11 is set to “0x80000000” and DMA transfer counter 12 is set to “0xC.”
Addresses “0x00000000” to “0x7FFFFFFF” are fixed as addresses of an internal bus while addresses “0x80000000” to “0xFFFFFFFF” are fixed as addresses of an external bus. DMA control unit 50 determines whether a transfer source address and a transfer destination address are in an internal bus or in an external bus, respectively, according to the most significant bit of the addresses stored in transfer source address register 10 and transfer destination address register 20.
In cycle 1, DMA control unit 50 asserts IREQ signal 115 of the internal bus and outputs the first transfer source address to IADDR [31:0] 110 so as to start a read access to the internal bus. At this time, DMA control unit 50 outputs a “H” to IRW signal 111 and gives notification of the read access.
In cycle 2, IREADY signal 114 of the internal bus becomes of “H” and notification is made that the internal bus access is completed. At the end of this cycle, DMA control unit 50 writes the value of IRDATA [31:0] 113 in FIFO memory 70.
In cycle 3, second read access is started with the internal bus, EREQ signal 125 is asserted to an external bus interface, the first transfer destination address is outputted to EADDR [31:0] 120, the data read out from FIFO memory 70 is outputted to EWDATA [31:0] 122 and a write access to the external bus interface is started. At this time, DMA control unit 50 outputs a “L” to ERW signal 121 and makes notification that the access is a write access. In this cycle 3, a “H” is outputted to EREADY signal 124 by the external bus interface so that notification is made that the external bus access is completed.
In the following, in the same manner as in the above, in cycle 4, the second read access to the internal bus is completed and the data from the internal bus is written into FIFO memory 70. In cycle 5, the third read access to the internal bus is started and the second write access to the external bus interface is carried out. In cycle 6, the third-time read access to the internal bus is completed and data from the internal bus is written into FIFO memory 70. In cycle 7, the third write access to the external bus interface is carried out so as to complete the DMA transfer.
FIG. 4 shows another example of a timing chart of a conventional DMA controller at the time of DMA transfer. In this timing chart, the write access to the external bus interface is carried out in a burst access mode. Here, “0x00000000” is set in transfer source address register 10, “0x80000000” is set in transfer destination address register 11 and “0x10” is set in DMA transfer counter 12. DMA control unit 50 determines whether a transfer source address and a transfer destination address are in an internal bus or in an external bus, respectively, according to the most significant bit of the addresses stored in transfer source address register 10 and transfer destination address register 11.
In cycle 2, DMA control unit 50 asserts IREQ signal 115 of the internal bus and outputs the first transfer source address to IADDR [31:0] 110 so as to start a read access to the internal bus. At this time, DMA control unit 50 outputs a “H” to IRW signal 111 and gives notification that the access is a read access. In this cycle, IREADY signal 114 of the internal bus becomes of “H” and notification is made that the internal bus access is completed. At the end of this cycle, DMA control unit 50 writes the value of IRDATA [31:0] 113 into FIFO memory 70.
In cycle 3, IADDR [31:0] 110 is updated and second read access to the internal bus is started. Similar operations are carried out in cycles 4 and 5 and four read accesses to the internal bus are carried out so that respective data is written into FIFO memory 70. At the end of cycle 5, IREQ signal 115 is negated and the read access to the internal bus is completed.
In cycle 6, DMA control unit 50 asserts EREQ signal 125 and EBURST signal 126 of the external bus and outputs the first transfer destination address to EADDR [31:0] 120 so that a write access to the external bus interface is started. At this time, DMA control unit 50 outputs a “L” to ERW signal 121 and makes a notification that this access is a write access. DMA control unit 50 reads out data stored in FIFO memory 70 and outputs the data to EWDATA [31:0] 122. In this cycle, EREADY signal 124 of the external bus becomes of “H” and notification is made that the external bus access is completed.
In cycle 7, EADDR [31:0] 120 is updated and second write access to the external bus is started. Similar operations are carried out in cycles 8 and 9 and the four write accesses to the external bus are carried out so that respective data stored in FIFO memory 70 is outputted to the external bus interface. At the end of cycle 9, EREQ signal 125 and EBURST signal 126 are negated and the write access to the external bus is completed.
However, in the case that a DMA transfer from the internal bus to the external bus is carried out by using the above described conventional DMA controller, FIFO memory 70 becomes indispensable when the burst access to the external bus is faster than the access to the internal bus. That is to say, when a DMA transfer from the internal bus to the external bus is attempted to be carried out without using FIFO memory 70, the speed of the read access to the internal bus cannot keep up with the speed of the burst access to the external bus so that failure of reading data occurs and correct data transfer cannot be carried out.
In addition, in the case that a DMA transfer from the external bus to the internal bus is carried out by using the above described conventional DMA controller, when the burst access to the external bus is faster than the access to the internal bus and when a DMA transfer from the external bus to the internal bus without using FIFO memory 70 is attempted to be carried out, the speed of the write access to the internal bus cannot keep up with the speed of the burst access to the external bus so that an overflow occurs and correct data transfer cannot be carried out.
In addition, in the conventional DMA controller the cycle number required for one access to the internal bus cannot be predicted and, therefore, in the case that a burst access is requested for the external bus interface, it is necessary to carry out a data transfer by using FIFO memory 70 regardless of the actual cycle number required for the access to the internal bus.
Furthermore, in the case that the amount of data to be transfer red by using FIFO memory 70, in particular the maximum amount of data to be transferred that is allowed in the DMA transfer, exceeds the capacity of FIFO memory 70, the control of the DMA transfer becomes complicated due to reasons such that it is necessary to carry out one DMA transfer request by dividing into a plurality of DMA transfers.
Because of the above reasons, there is a problem that an expensive FIFO memory 70 must be mounted in the DMA controller and the cost for the DMA controller becomes high.